1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming 3D semiconductor devices, such as FinFET devices, by performing a liner recessing process to define the fin height of the FinFET device, and to a FinFET device that includes such a recessed liner structure.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
One process flow that is typically performed to form FinFET devices involves forming a plurality of trenches in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins. These trenches are typically formed in the substrate during the same process operation for processing simplicity. The trenches have a target depth that is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. Thereafter, a chemical mechanical polishing (CMP) process is then performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins, which corresponds to the final fin height of the fins.
Some integrated circuit products contain FinFET devices that have a different fin pitch, i.e., different fin spacing. FIG. 1A schematically depicts an illustrative prior art integrated circuit product 10 at a point of fabrication wherein a plurality of trenches 12 have been formed in a bulk semiconducting substrate 14 by performing an etching process through a patterned hard mask layer 16, e.g., a patterned layer of silicon dioxide. The etching process results in the formation of a plurality of fins 20. The product 10 comprises a region 20N where the FinFET devices have fins with a relatively narrow fin pitch 22N, e.g., 20-50 nm, and another region 20W where the FinFET devices have fins with a relatively wide fin pitch 22W, e.g., 1 μm or more. These regions are typically spaced apart on the substrate 14.
FIG. 1B depicts the product 10 after the patterned hard mask layer 16 has been removed, a layer of insulating material 24, e.g., silicon dioxide, has been deposited so as to overfill the trenches and a CMP process has been performed on the layer of insulating material in an effort to planarize the upper surface of the layer of insulating material 24 with the upper surface of the fins 20. As a result of the relatively wider fin pitch in the area 20W, there may be more dishing 26 in the region 20W than in the region 20N having the narrower fin pitch.
FIG. 1C depicts the prior art product 10 at a point in fabrication wherein a timed etching process has been performed on the layer of insulating material 24 to reduce its thickness and thereby define a reduced-thickness layer of insulating material 24R. Typically, semiconductor manufacturers try to establish the final height of the fins for the FinFET devices by controlling this etching process and the resulting thickness of the reduced-thickness layer of insulating material 24R.
There are several problems with the aforementioned process of forming fins for FinFET semiconductor devices. More specifically, as depicted in FIG. 1C, such a process flow may produce fins with varying heights 28A, 28B and 28C across the substrate. Such variations in fin height are undesirable from a design, manufacturing and performance standpoint. For example, if the fin height on a FinFET device is less than the target fin height determined by the design process, the resulting FinFET device may not produce as large of drive current as is anticipated by the circuit designer and the circuit may not function as well as anticipated. Having fins with differing height levels can also make manufacturing more difficult in that it becomes more difficult to achieve a planar surface in subsequent processing operations.
Such differences in fin height may be the result, at least in part, of several factors. Since the etching process that is performed to recess the layer of insulating material 24R (see FIG. 1C) is a timed etching process, there are variations in the resulting thickness of the reduced-thickness layer of insulating material 24R. Another factor that contributes to this undesirable situation may be excessive dishing 26 of the layer of insulating material 24 during the CMP process depicted in FIG. 1B. As a result of such dishing 26, after the recess etch process is performed, the fins in areas where such dishing is present may have a fin height that is greater than the target fin height due to the reduction in thickness of the layer of insulating material 24 as a result of the excessive dishing. Additionally, the initial depth of the trenches 12 in the region 20N may be different than the depth of the trenches 12 in the region 20W due to the difference in fin pitch in those two regions.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production cost relative to previous device generations. Thus, device designers spend a great amount of time in an effort to maximize device performance while seeking ways to reduce manufacturing cost and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices.
The present disclosure is directed to various methods of forming 3D semiconductor devices, such as FinFET devices, by performing a liner recessing process to define the fin height of the FinFET devices, and to a FinFET device that includes such a recessed liner structure, that may solve or reduce one or more of the problems identified above.